Microelectronic packages with small footprints and associated methods of manufacturing

ABSTRACT

Several embodiments of stacked-die microelectronic packages with small footprints and associated methods of manufacturing are disclosed herein. In one embodiment, the package includes a substrate, a first die carried by the substrate, and a second die between the first die and the substrate. The first die has a first footprint, and the second die has a second footprint that is smaller than the first footprint of the first die. The package further includes an adhesive having a first portion adjacent to a second portion. The first portion is between the first die and the second die, and the second portion being between the first die and the substrate.

TECHNICAL FIELD

The present disclosure is related to stacked-die microelectronicpackages with small footprints and associated methods of manufacturing.

BACKGROUND

Microelectronic dies are typically manufactured on semiconductor wafersor other types of workpieces using sophisticated equipment andprocesses. The individual dies generally include a plurality ofbond-pads coupled to integrated circuits. The bond-pads provide externalcontacts through which supply voltage, data signals, and otherelectrical signals are transmitted to/from the integrated circuits. Thebond-pads are usually very small, and they are typically arranged indense arrays separated by a fine pitch. The wafers and dies can also bequite delicate. As a result, the dies are packaged for protection andfor connecting the bond-pads to arrays of larger terminals that can besoldered to printed circuit boards.

One challenge of manufacturing microelectronic devices is to costeffectively package the dies. Electronic product manufacturers are undercontinuous pressure to reduce the size of their products. Accordingly,microelectronic die manufacturers seek to reduce the size of thepackaged dies incorporated into the electronic products. FIG. 1illustrates an existing microelectronic device package 100 havingstacked dies. As shown in FIG. 1, the package 100 includes a substrate101 carrying a first die 102 a and a second die 102 b encapsulated in anencapsulant 106. The first die 102 a has a larger footprint than thesecond die 102 b. A first adhesive 104 a couples the first die 102 a toa first surface 101 a of the substrate 101. A second adhesive 104 bcouples the second die 102 b to the first die 102 a. The substrate 101also includes first terminals 108 a that are inboard of second terminals108 b on the first surface 101 a. First wirebonds 110 a extend betweenfirst terminals 108 a on the substrate 101 and first bond sites 112 a onthe first die 102 a. Second wirebonds 110 b extend between secondterminals 108 b on the substrate 101 and second bond sites 112 b on thesecond die 102 b. The package 100 also includes a plurality of solderballs 114 attached to a second surface 101 b of the substrate 101. Aplurality of traces 116 of the substrate 101 electrically coupleindividual solder balls 114 to the first and second terminals 108 a and108 b.

The microelectronic device package 100 typically has a large footprintto accommodate the wirebonding of the second die 102 b to the substrate101. As shown in FIG. 1, the second wirebonds 110 b must have sufficientclearance from the first die 102 a and/or the first wirebonds 110 a forthe package 100 to function properly. To have sufficient clearance, thesecond wirebonds 110 b need to have a large loop height, and the firstand second terminals 108 a and 108 b need to have a large separationtherebetween. Thus, the package 100 typically has both a large height Hand a large width W that result in a large footprint. Accordingly, thereis a need for structural arrangements that can reduce the footprint ofmicroelectronic device packages.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partially schematic cross-sectional view of amicroelectronic device package in accordance with the prior art.

FIG. 2 is a partially schematic cross-sectional view of amicroelectronic device package having a small footprint in accordancewith an embodiment of the disclosure.

FIGS. 3A-3D illustrate a process of forming the microelectronic devicepackage shown in FIG. 2 in accordance with an embodiment of thedisclosure.

FIG. 4 is a partially schematic cross-sectional view of amicroelectronic device package having a small footprint in accordancewith another embodiment of the disclosure.

FIG. 5 is a partially schematic cross-sectional view of amicroelectronic device package having a small footprint in accordancewith a further embodiment of the disclosure.

FIG. 6 is a schematic diagram of a system that includes one or moremicroelectronic device packages in accordance with embodiments of thedisclosure.

DETAILED DESCRIPTION

Specific details of several embodiments of the disclosure are describedbelow with reference to microelectronic device packages with smallfootprints and associated methods of manufacturing. Typicalmicroelectronic device packages include microelectronic circuits orcomponents, thin-film recording heads, data storage elements,microfluidic devices, and other components manufactured onmicroelectronic substrates. Micromachines and micromechanical devicesare included within this definition because they are manufactured usingtechnology similar to that used in the fabrication of integratedcircuits. Substrates can be semiconductor pieces (e.g., doped siliconwafers or gallium arsenide wafers), non-conductive pieces (e.g., variousceramic substrates), or conductive pieces. A person skilled in therelevant art will also understand that the disclosure may haveadditional embodiments, and that the disclosure may be practiced withoutseveral of the details of the embodiments described below with referenceto FIGS. 2-6.

FIG. 2 is a partially schematic cross-sectional view of amicroelectronic device package 200 having a small footprint inaccordance with an embodiment of the disclosure. As shown in FIG. 2, themicroelectronic device package 200 can include a substrate 201, a firstdie 202 a and a second die 202 b carried by the substrate 201, and anencapsulant 206 encapsulating the first and second dies 202 a and 202 b.The substrate 201 can include first terminals 208 a that are outboard ofsecond terminals 208 b on a first surface 201 a. The substrate 201 canalso carry a plurality of solder balls 214 on a second surface 201 bopposite the first surface 201 a. A plurality of traces 216 of thesubstrate 201 electrically couple individual solder balls 214 to thefirst and second terminals 208 a and 208 b.

The first die 202 a includes a first active surface 203 a opposite afirst backside surface 203 b. The second die 202 b includes a secondactive surface 205 a opposite a second backside surface 205 b. The firstdie 202 a can be an upper die, and the second die 202 b can be a lowerdie. The first die 202 a has a first footprint (e.g., as characterizedby a width, a length, a diameter, and/or another dimension) larger thana second footprint of the second die 202 b. In certain embodiments, thesecond footprint of the second die 202 b can be substantially within thefirst footprint of the first die 202 a. For example, in the illustratedembodiment, the first and second footprints are generally centeredrelative to each other. In other embodiments, the second footprint maybe offset from the first footprint of the first die 202 a. In aparticular embodiment, the first die 202 a includes a memory device(e.g., DRAM), and the second die 202 b includes a logic processor and/orother suitable processing components. In other embodiments, the firstand second dies 202 a and 202 b can include other electrical and/ormechanical components.

The microelectronic device package 200 can also include first wirebonds210 a between first terminals 208 a on the substrate 201 and first bondsites 212 a on the first die 202 a. Second wirebonds 210 b extendbetween second terminals 208 b on the substrate 201 and second bondsites 212 b on the second die 202 b. The first wirebonds 210 a areoutboard of the corresponding second wirebonds 210 b. The firstwirebonds 210 a also have a first wirebond length greater than a secondwirebond length of the second wirebonds 210 b.

The microelectronic device package 200 can also include a first adhesive204 a and a second adhesive 204 b. The first adhesive 204 a is disposedbetween the first backside surface 203 b of the first die 202 a and thesecond active surface 205 a of the second die 202 b. The first adhesive204 a is also disposed between the first surface 201 a of the substrate201 and the perimeter portion of the first backside surface 203 b thatextends laterally beyond the second footprint of the second die 202 b.The second adhesive 204 b (e.g., an epoxy) is disposed between thesecond backside 205 b of the second die 202 b and the first surface 201a of the substrate 201. In certain embodiments, the first adhesive 204 acan include a film-over-wire adhesive and/or other suitable types ofadhesive. One suitable film-over-wire adhesive includes a die-attachfilm (Model No. ELEP MOUNT EM-310) provided by Nitto Denko Corp. ofOsaka, Japan. In other embodiments, the first adhesive 204 a can includean epoxy and/or other non-conductive material.

In certain embodiments, the first adhesive 204 a can substantially oreven completely encapsulate the second die 202 b, the second wirebonds210 b, the second bond sites 212 b, and the second terminals 208 b. Forexample, the first adhesive 204 a can include a first portion 207 aadjacent to and outboard of a second portion 207 b. The first portion207 a is between the first die 202 a and the substrate 201. The secondportion 207 b is between the first die 202 a and the second die 202 band generally corresponds to the second footprint of the second die 202b. The first portion 207 a couples the first die 202 a to the substrate201, and the second portion 207 b couples the first die 202 a to thesecond die 202 b. The first portion 207 a has a thickness greater thanthat of the second portion 207 b.

The first adhesive 204 a can have an overall height greater than thecombined height of the second die 202 b, the second adhesive 204 b, andthe loop height of the second wirebonds 210 b. The phrase “loop height”generally refers to the height between the top of a wirebond and thesurface of a corresponding die. The first adhesive 204 a can also havean overall width greater than that of the second die 202 b and thedistance between the second terminals 208 a such that the secondterminals 208 a are at least proximately inboard of the first die 202 a.In the illustrated embodiment, the first adhesive 204 a has a footprintgenerally equal to that of the first die 202 a. In other embodiments,the first adhesive 204 a can also have a footprint that is greater orless than that of the first die 202 a. In further embodiments, the firstadhesive 204 a can partially encapsulate at least one of the secondterminals 208 b and the second wirebonds 210 b. In yet furtherembodiments, the package 200 can include additional non-conductivelayers between the first and second dies 202 a and 202 b, as describedin more detailed below with reference to FIG. 4.

Several embodiments of the package 200 can have a smaller footprint andshorter wirebond lengths than in conventional packages (e.g., thepackage 100 shown in FIG. 1) because the second wirebonds 210 b areinboard of the first wirebonds 210 a. For example, the width of thepackage 200 and the length of the second wirebonds 210 b can be reducedbecause the second wirebonds 210 b do not extend outward beyond thefirst wirebonds 210 a. The height of the package 200 can also be reducedbecause the second wirebonds 210 b need not clear the first wirebonds210 a.

Several embodiments of the package 200 can also enable wirebonding thesecond die 202 b with a bond site layout that is more flexible than inconventional packages. For example, in the package 100 of FIG. 1, thesecond die 102 b is typically positioned at a corner of the first die102 a to enable ready wirebonding to the substrate 101 (FIG. 1). As aresult, the second die 102 b typically has an “I” shaped or an “L”shaped bond site layout, which may limit the overall wiring layout ofthe package 100. Accordingly, by positioning the second die 202 binboard the first die 202 a, the second die 202 b can have any desiredbond site layouts. For example, the second die 202 b can have bond sitessubstantially around its entire periphery.

Several embodiments of the package 200 can further reduce electricaland/or electromagnetic interference between the first and second dies202 a and 202 b. The inventors have recognized that the second die 102 bin FIG. 1 positioned proximate to an edge of the first die 102 a cancause a shift in supply and/or signal voltage in peripheral circuits inthe first die 102 a, and thus adversely affect the performance of thepackage 100. Accordingly, by positioning the second die 202 b away fromthe edges of the first die 202 a, such electrical and/or electromagneticinterference can be at least reduced.

FIGS. 3A-3D illustrate stages of a process for forming themicroelectronic device package 200 of FIG. 2 in accordance with anembodiment of the disclosure. FIG. 3A illustrates an early stage of theprocess that includes attaching the second die 202 b to the firstsurface 201 a of the substrate 201 with the second adhesive 204 b. FIG.3B illustrates a subsequent stage of the process that includeswirebonding the second die 202 b to the substrate 201. As a result, thesecond wirebonds 210 b extend between the second bond sites 212 b andthe corresponding second terminals 208 b.

FIG. 3C illustrates another stage of the process that includes applyingthe first adhesive 204 a to the first backside surface 203 b of thefirst die 202 a and attaching the first die 202 a to the substrate 201such that the first die 202 a is above the second die 202 b with thefirst adhesive 204 a therebetween. The first adhesive 204 a can includea film-over-wire adhesive and/or other suitable non-conductive material.In one embodiment, the first adhesive 204 a can be applied at atemperature of about 120° C. and can be cooled and/or otherwise hardenedafter being placed on the second die 202 b. In other embodiments, thefirst adhesive 204 a can be applied at other suitable temperatures. Inany of the foregoing embodiments, the first adhesive 204 a can at leastpartially encapsulate the second die 202 b, the second wirebonds 210 b,and the second bond sites 212 b.

As illustrated in FIG. 3D, further stages of the process can includewirebonding the first die 202 a to the substrate 201. As a result, thefirst wirebonds 210 a extend between the first bond sites 212 a and thecorresponding first terminals 208 a. The process can further includeencapsulating the first die 202 a, the second die 202 b, and thesubstrate 201 in the encapsulant 206 utilizing injection molding and/oranother suitable encapsulating process and attaching the solder balls214 to the second surface 201 b of the substrate 201, as shown in FIG.2.

Several embodiments of the process described above with reference toFIGS. 3A-3D can reduce the risk of mold voiding in manufacturing thepackage 200. The inventors have recognized that the pyramid-likearrangement of the first and second dies 102 a and 102 b of FIG. 1 maydisrupt the laminar flow of the encapsulant 106 during a moldingprocess. This disruption can form voids in the encapsulant 106, and thusreduce the structural integrity of the package 100. As a result, byencapsulating the second die 202 b within the first adhesive 204 a, thedisruption to the laminar flow of the encapsulant 206 can be reduced oravoided.

The process described above with reference to FIGS. 3A-3D can haveadditional and/or different process stages. For example, in certainembodiments, the first adhesive 204 a does not completely encapsulatethe second die 202 b, the second wirebonds 210 b, and the second bondsites 212 b. Instead, as illustrated in FIG. 4, a non-conductive layer218 (e.g., an epoxy) is formed between the first and second dies 202 aand 202 b via injection molding, transfer molding, and/or anothersuitable encapsulation process. The non-conductive layer 218 can atleast partially encapsulate the second die 202 b, the second wirebonds210 b, and the second bond sites 212 b. The process can then includeattaching the first die 202 a to the non-conductive layer 218 with thefirst adhesive 204 a. In certain embodiments, the non-conductive layer218 can have a composition different than the first adhesive 204 a. Inother embodiments, the non-conductive layer 218 can have a compositionthat is at least generally similar to the first adhesive 204 a.

In further embodiments, the first die 202 a, the second die 202 b, andthe substrate 201 can have other arrangements. For example, asillustrated in FIG. 5, the second die 202 b can have a flip-chiparrangement relative to the substrate 201. A plurality of conductivemembers 220 (e.g., solder balls, solder bumps, or pillar bumps) cancouple the second bond sites 212 b of the second die 202 b to the secondterminals 208 b on the substrate 201. As a result, the second wirebonds210 b (FIG. 2) can be omitted. In yet further embodiments, the package200 can have other desired arrangements.

Even though only one first die 202 a is illustrated in FIGS. 2-5, incertain embodiments, the package 200 can include two, three, four,and/or any desired number of first dies 202 a attached to one anotherwith an adhesive in a stacked arrangement. In further embodiments, thepackage 200 can also include additional second dies 202 b. For example,one second die 202 b can be disposed below the first die 202 a andanother second die 202 b can disposed above the first die 202 a. Infurther embodiments, multiple first and second dies 202 a and 202 b canbe arranged alternatively in a stack.

Individual microelectronic device packages 200 may be incorporated intomyriad larger and/or more complex systems. A representative system 300is shown schematically in FIG. 6. The system 300 can include a processor301, a memory 302, input/output devices 303, and/or other subsystems orcomponents 304. The resulting system 300 can perform a wide variety ofcomputing, processing, storage, sensor, and/or other functions.Accordingly, the representative system 300 can include, withoutlimitation, computers and/or other data processors, for example, desktopcomputers, laptop computers, Internet appliances, and hand-held devices(e.g., palm-top computers, wearable computers, cellular or mobilephones, multi-processor systems, processor-based or programmableconsumer electronics, network computers, mini computers). Therepresentative system 300 can also include servers and associated serversubsystems, display devices, and/or memory devices. Components of thesystem 300 may be housed in a single unit or distributed over multiple,interconnected units, e.g., through a communications network. Componentscan accordingly include local and/or remote memory storage devices andany of a wide variety of computer-readable media, including magnetic oroptically readable or removable computer disks.

From the foregoing, it will be appreciated that specific embodiments ofthe disclosure have been described herein for purposes of illustration,but that various modifications may be made without deviating from thedisclosure. For example, many of the members of one embodiment may becombined with other embodiments in addition to or in lieu of the membersof the other embodiments. Accordingly, the disclosure is not limitedexcept as by the appended claims.

1. A microelectronic device package, comprising: a substrate having afirst terminal and a second terminal on a surface of the substrate, thefirst terminal being outboard of the second terminal; a first die spacedapart from the first surface of the substrate and having a first bondsite; a first wirebond between the first bond site and the firstterminal; a second die between the first die and the first surface ofthe substrate and having a second bond site; a second wirebond betweenthe second bond site and the second terminal; and an adhesive at leastpartially between the first die and the first surface of the substrate,the adhesive at least substantially encapsulating the second die, thesecond terminal, and the second wirebond.
 2. The microelectronic devicepackage of claim 1 wherein the surface is a first surface of thesubstrate and the adhesive is a first adhesive including a film-on-wireadhesive, and wherein the substrate further includes a plurality ofsolder balls on a second surface opposite the first surface and aplurality of traces between the first and second terminals and thecorresponding solder balls, and further wherein the microelectronicdevice package further includes a second adhesive between the second dieand the first surface of the substrate, and yet further wherein thefirst adhesive substantially encapsulates the second die, the secondterminal, the second wirebond, and the second adhesive.
 3. Themicroelectronic device package of claim 1 wherein the adhesive includesa first portion between the first die and the surface of the substrateand a second portion between the first die and the second die, the firstportion having a thickness greater than that of the second portion. 4.The microelectronic device package of claim 1 wherein the adhesiveincludes a first portion between the first die and the surface of thesubstrate and a second portion between the first die and the second die,the first portion being outboard of the second die.
 5. Themicroelectronic device package of claim 1 wherein the adhesive includesa first portion between the first die and the surface of the substrateand a second portion between the first die and the second die, andwherein the first portion is configured to couple the first die to thesubstrate, and further wherein the second portion is configured tocouple the first die to the second die.
 6. The microelectronic devicepackage of claim 1 wherein the adhesive is a first adhesive, and whereinthe microelectronic device package further includes a second adhesivebetween the second die and the first surface of the substrate, andfurther wherein the first adhesive has a height greater than a sum of aheight of the second die, a height of the second adhesive, and a loopheight of the second wirebond.
 7. The microelectronic device package ofclaim 1 wherein the adhesive includes a film-on-wire adhesive.
 8. Amicroelectronic device package, comprising: a substrate; a first diecarried by the substrate, the first die having a first footprint; asecond die between the first die and the substrate, the second diehaving a second footprint that is smaller than the first footprint ofthe first die; and an adhesive having a first portion adjacent to asecond portion, the first portion being between the first die and thesecond die and the second portion being between the first die and thesubstrate.
 9. The microelectronic device package of claim 8 wherein thesubstrate includes a first terminal and a second terminal spaced apartfrom the first terminal on a first surface and a plurality of solderballs on a second surface opposite the first surface, and wherein thefirst die includes a first bond site on a first active surface and afirst backside surface opposite the first active surface, and whereinthe second die includes a second bond site on a second active surfaceand a second backside surface opposite the second active surface, thesecond active surface facing the first backside surface, and wherein thefirst portion of the adhesive is a central portion directly between thefirst backside surface of the first die and the first surface of thesubstrate, and wherein the second portion of the adhesive is aperipheral portion outside of the central portion such that the secondportion of the adhesive is directly between the first backside surfaceof the first die and the second active surface of the second die, andfurther wherein the microelectronic device package includes a firstwirebond between the first terminal and the first bond site; a secondwirebond between the second terminal and the second bond site, the firstwirebond being outboard of the second wirebond.
 10. The microelectronicdevice package of claim 8 wherein the second footprint of the second dieis within the first footprint of the first die.
 11. The microelectronicdevice package of claim 8 wherein the first and second footprints aregenerally centered relative to each other.
 12. The microelectronicdevice package of claim 8 wherein the second portion of the adhesive hasa footprint generally corresponding to the second footprint of thesecond die.
 13. The microelectronic device package of claim 8 whereinthe substrate includes a first terminal and a second terminal spacedapart from the first terminal, and wherein the first die includes afirst bond site and the second die includes a second bond site, andwherein the microelectronic device package includes a first wirebondbetween the first terminal and the first bond site and a second wirebondbetween the second terminal and the second bond site, the first wirebondbeing outboard of the second wirebond.
 14. The microelectronic devicepackage of claim 8 wherein the substrate includes a first terminal and asecond terminal spaced apart from the first terminal, and wherein thefirst die includes a first bond site and the second die includes asecond bond site, and wherein the microelectronic device packageincludes a wirebond between the first terminal and the first bond siteand a solder ball between the second terminal and the second bond site,the first wirebond being outboard of the solder ball.
 15. Themicroelectronic device package of claim 8, further comprising anon-conductive layer between the adhesive and the second die and betweenthe adhesive and the substrate, the non-conductive layer substantiallyencapsulating the second die.
 16. A method for assembling amicroelectronic device package, comprising: applying an adhesive to afirst backside surface of a first die, the first die having a firstactive surface opposite the first backside surface; attaching a seconddie to a surface of a substrate; positioning the first backside surfaceof the first die to be superimposed with the second die with theadhesive applied on the first backside surface; and at leastsubstantially encapsulating the second die with the adhesive on thefirst backside surface of the first die, wherein the first backsidesurface of the first die is spaced apart from the second die.
 17. Themethod of claim 16 wherein the first die includes a first bond site onthe first active surface, and wherein the second die includes a secondbond site on a second active surface facing the first backside surface,and further wherein the substrate includes a first terminal outboard ofa second terminal on the surface, and further wherein the method alsoincludes placing a first wirebond between the first terminal and thefirst bond site; placing a second wirebond between the second terminaland the second bond site, the second wirebond being inboard of the firstwirebond; at least substantially encapsulating the second wirebond andthe second terminal with the adhesive on the first backside surface ofthe first die; and encapsulating the first die, the adhesive, the seconddie, the first wirebond, and the second wirebond with an encapsulant.18. The method of claim 16 wherein the first die includes a first bondsite on the first active surface, and wherein the second die includes asecond bond site on a second active surface facing away from the firstbackside surface, and further wherein the substrate includes a firstterminal outboard of a second terminal on the surface, and furtherwherein the method also includes placing a wirebond between the firstterminal and the first bond site; coupling the second terminal to thesecond bond site with a solder ball; at least substantiallyencapsulating the solder ball and the second terminal with the adhesiveon the first backside surface of the first die; and encapsulating thefirst die, the adhesive, the second die, the wirebond, and the solderball with an encapsulant.
 19. The method of claim 16, further comprisingattaching the first die to the second die and the substrate with theadhesive on the first backside surface of the first die.
 20. The methodof claim 16 wherein applying an adhesive includes applying an adhesivehaving a footprint generally equal to a first footprint of the first dieto the first backside surface of the first die, and whereinsubstantially encapsulating the second die includes substantiallyencapsulating the second die with the adhesive on the first backsidesurface of the first die, the second die having a second footprint lessthan the first footprint.
 21. The method of claim 16 wherein applying anadhesive includes applying an adhesive having a footprint generallyequal to a first footprint of the first die to the first backsidesurface of the first die, and wherein substantially encapsulating thesecond die includes substantially encapsulating the second die with theadhesive on the first backside surface of the first die, the second diehaving a second footprint less than and within the first footprint. 22.The method of claim 16 wherein applying an adhesive includes applying anadhesive having a footprint generally equal to a first footprint of thefirst die to the first backside surface of the first die, and whereinsubstantially encapsulating the second die includes substantiallyencapsulating the second die with the adhesive on the first backsidesurface of the first die, the second die having a second footprint lessthan and generally centered with the first footprint.
 23. A method forassembling a microelectronic device package, comprising: applying afirst adhesive to a first die having a first footprint; attaching asecond die to a substrate with a second adhesive, the second die havinga footprint smaller than the first footprint of the first die; disposinga non-conductive material between the first die and the substrate; andencapsulating the second die with the non-conductive material betweenthe first die and the substrate.
 24. The method of claim 23 whereindisposing a non-conductive material includes disposing the firstadhesive applied on the first die onto the second die, and whereinencapsulating the second die with the non-conductive material includesencapsulating the second die with the first adhesive.
 25. The method ofclaim 23 wherein encapsulating the second die with the non-conductivematerial includes encapsulating the second die with the non-conductivematerial having a composition different than the first adhesive.